Last night’s CoreWeave × Cognition Vera Rubin note was a neocloud production ticket — limited NVL72 availability with customer SWE-2 / RL deltas vs GB200. Yesterday morning’s Claude Sonnet 5.5 note was a routing ticket. The live Lightbits Inferra and Astera Leo X posts already answered two sides of the post-HBM memory ladder: prefetch orchestration across tiers and fabric-attached DDR for warm KV. On September 29, 2026 (Business Wire; HPCwire dated Sep 30), Everspin demonstrated what it calls the world’s first CXL-connected MRAM platform at SNIA Developer Conference 2026. This morning is that persistent media on CXL board — a working demo you can aim checkpointing and persistent KV experiments at, not another orchestration or fabric-controller rematch.
Primary source: Everspin Business Wire release (FinancialContent). Secondary reprint: HPCwire off-the-wire. Product context: Everspin data-center applications and the FLIT-MRAM / CXL persistence page. Specs and speed claims below are vendor claims from the SDC demo release unless noted.
Spec sheet (named numbers)
| Everspin PERSYST CXL MRAM | |
|---|---|
| Announcement / demo | September 29–30, 2026 — SNIA Developer Conference (SDC) 2026 |
| Claim | World’s first CXL-connected MRAM platform (Everspin) |
| Memory product | Everspin PERSYST 1GB DDR4 MRAM UDIMMs |
| Server | Supermicro AS-1116CS-TN |
| Host CPU | AMD EPYC 9355 (32-core) |
| CXL endpoint | AMD Alveo U250 FPGA + Wolley CXL controller |
| Access model | Memory-semantic persistent memory over CXL (not block SSD semantics) |
| Latency framing | Cache-line-level, nanosecond-class access (vendor) |
| Write claim | Up to 100× faster writes vs NAND-based SSD (vendor) |
| Persistence | Retains data through power loss / restart — no battery-backed DRAM, no mandatory flush-to-SSD |
| Pooling | Memory resources can be pooled and shared across hosts (vendor) |
| AI workloads named | Checkpointing; persistent key-value (KV) cache |
| Status | Working demo; ready for customer workload testing — not a disclosed shipping appliance SKU or capacity roadmap |
That is a different purchase sentence from Inferra’s when do I prefetch the next KV block and Leo X’s attach DDR to the accelerator fabric. This one is: is there a working open-standards path that puts magnetoresistive persistent media on CXL with memory semantics, and what BOM do I need to reproduce the demo.
What the demo actually is
Everspin and Wolley showed read and write access to PERSYST MRAM through the CXL interface under what they describe as demanding test conditions. The configuration is explicit enough to put on a lab whiteboard:
- Host — Supermicro AS-1116CS-TN with EPYC 9355.
- CXL bridge — Alveo U250 carrying a Wolley CXL controller (FPGA endpoint, not a sealed Everspin CXL ASIC appliance).
- Media — PERSYST 1GB DDR4 MRAM UDIMMs.
The architectural claim is the interesting part for people who already run CXL expanders and KV tiers. MRAM keeps state without power. CXL gives coherent, memory-semantic attachment instead of treating the device like another SSD. Together, Everspin’s pitch is a fast persistent buffer/cache tier between DRAM and NAND: survive a power hit without supercaps or battery-backed DRAM, and without waiting for a flush path to flash.
Sanjeev Aggarwal’s quote in the release is marketing-adjacent, but the operational sentence underneath it is the one I care about: they now have a working system so customers can run their own workloads and measure benefit — not a slide of theoretical endurance curves.
Where it sits next to Inferra, Leo X, and NVHBM
| Purchase | Product | What it buys |
|---|---|---|
| Prefetch / orchestration across HBM→DRAM→NVMe | Lightbits Inferra | SLSAP timing; published TTFT multiples on long restores |
| Fabric-attached DDR for warm KV | Astera Leo X | Scorpio-side expanders; vendor 62% warm TTFT / 22% TPS claims |
| HBM capacity / bandwidth roadmaps | NVHBM and related HBM notes | On-package high-bandwidth working set |
| Persistent CXL MRAM media (demo) | Everspin PERSYST + Wolley | Memory-semantic persistence; 1GB UDIMM demo; 100× write claim vs NAND |
Do not collapse this into Inferra or Leo X. Inferra answers when to move blocks. Leo X answers where DDR attaches relative to the accelerator fabric. Everspin answers what media stays hot and coherent across power events if you want persistence without battery DRAM or a NAND write buffer.
The AI-specific callouts in the SDC release are checkpointing and persistent KV cache — the same problem class as Inferra/Leo X, one tier down the stack into the media itself. Capacity is still demo-scale: 1GB UDIMMs. That is enough to prove the CXL path and to prototype metadata, small persistent caches, or checkpoint scratch — not enough to hold a multi-hundred-GB KV working set. Treat the demo as a media + interconnect proof, then ask Everspin/Wolley what capacity and controller roadmap sits behind customer testing.
Caveats
- Demo ≠ shipping SKU. The release says ready for customer workload testing. There is no public appliance part number, rack BOM, or capacity ladder in the SDC note.
- 1GB is not a fleet KV tier. Compare against Leo X’s up-to-2TB-per-device class claims and Inferra’s multi-tier virtualization. This morning’s durable fact is the CXL+MRAM path, not terabytes of persistent media.
- 100× vs NAND is a vendor write claim. Reproduce under your IO size, queue depth, and persistence mode before you reprice a write buffer or checkpoint path.
- Nanosecond-class / cache-line framing is marketing language until you measure load-to-use on the Alveo/Wolley path vs local DDR5 and vs a CXL DRAM expander.
- FPGA CXL endpoint. Alveo U250 + Wolley is a flexible demo path; ask what the production controller looks like (ASIC vs continued FPGA) before you design a SKU around it.
- Not a rematch of CoreWeave NVL72, Sonnet 5.5, Helios $1.2B, or Volantis $88M. Those are production GPU, mid-tier model, procurement, and 2027 photonic funding boards. This is the persistent CXL MRAM demo.
How I would evaluate
- Reproduce the BOM — AS-1116CS-TN + EPYC 9355 + U250/Wolley + PERSYST 1GB; confirm the CXL.mem path and persistence across controlled power pulls.
- Checkpoint microbench — measure time-to-durable for small model/optimizer shards vs battery-DRAM + SSD flush and vs CXL DRAM without persistence.
- Persistent KV prototype — pin a hot metadata or prefix-KV working set that must survive restart; compare restart TTFT and correctness against Inferra-style restore from NVMe and Leo-style warm DDR.
- Capacity ask — get the next UDIMM/module sizes and whether pooling across hosts is software-visible the way the release implies.
- Keep boards separate — Inferra for prefetch policy, Leo X for fabric-attached DDR, Everspin for persistent MRAM on CXL. Do not merge them into one “memory wall” post.
Bottom line
At SNIA SDC 2026 (September 29–30 window), Everspin demonstrated a working CXL-connected PERSYST MRAM platform: Supermicro AS-1116CS-TN, EPYC 9355, Alveo U250 + Wolley CXL, and PERSYST 1GB DDR4 MRAM UDIMMs, with vendor claims of memory-semantic access, up to 100× writes vs NAND SSD, power-loss persistence without battery DRAM, and explicit AI targets in checkpointing and persistent KV cache. Durable facts are the named BOM, the demo status (customer workload testing), and the separation from Inferra’s orchestration board and Leo X’s fabric-DDR board. Capacity is still 1GB-class — measure before you invent a fleet tier — but the CXL+MRAM path is now something you can put hands on, not only a FLIT-MRAM architecture page.
Create-only. Specs from Everspin’s Sep 29 Business Wire SDC release and related Everspin product pages. Update when Everspin publishes a shipping CXL MRAM SKU, capacity roadmap, or third-party customer benches under a common checkpoint/KV harness.
Sources: Everspin Business Wire (FinancialContent) · HPCwire · Everspin data centers · FLIT-MRAM / CXL.
Anpoo Sivanadi, Staff Software Engineer