AMD Helios UALoE: Open Scale-Up on Ethernet, With the Bridge Caveats

Yesterday I wrote about NVIDIA NVHBM — moving the memory controller into the HBM base die for NVLink Fusion partners. The open counterweight is not another GPU SKU. It is AMD Helios: 72× Instinct MI455X GPUs in one rack, glued together with UALink-over-Ethernet (UALoE) until native UALink switch silicon is volume-ready.

I am reading Helios as a scale-up fabric story first, and a GPU story second. The MI455X numbers are real and large. The question a cluster reader should ask is whether the fabric those GPUs sit on is production Ethernet bridging a still-maturing open standard — or a proprietary switch you already know how to operate.

Spec sheet (named numbers)

Primary sources: AMD Helios newsroom, AMD Helios scale-up networking blog, ServeTheHome Hot Chips MI400, Phoronix UALink patches v2, TechTimes NVLink Fusion vs UALink.

What Helios is actually selling

Helios is AMD’s rack-shaped answer to NVIDIA’s NVL72-class domains. The building block is a compute tray: four MI455X EAMs, one EPYC 9006 host, UALoE for scale-up, Pensando NICs for scale-out. Eighteen trays make the 72-GPU rack.

AMD’s competitive claims (AMD Performance Labs modeling, footnotes on the newsroom post) vs a Vera Rubin NVL72 reference include roughly 15% more peak FP4, 50% more HBM capacity, 6% more HBM bandwidth, 50% more scale-out bandwidth, and up to 30% more tokens per dollar on a Kimi K2 Thinking ISL/OSL 32K/8K model. Treat those as vendor comparisons, not independent InferenceX curves. The absolute rack numbers — 31 TB HBM, 1.7 PB/s, 2.9 EFLOPS FP4, 260 TB/s scale-up — are the ones I keep for capacity math.

Hot Chips filled in the silicon. MI455X moves from MI355X’s 288 GB HBM3E to 432 GB HBM4 (~1.5× capacity) with roughly 2.9× HBM bandwidth in AMD’s framing. Peak MXFP4 is listed at 40.26 PFLOPS on a 256-WGP design. Measured ROCm.AI slides AMD showed include 20 TB/s MLA decode bandwidth in FP8 and 20 PFLOPS FP4 compute — again vendor measurements, useful as generation-over-generation deltas against MI355X, not as a substitute for a third-party rack suite.

UALoE is the interesting half

Scale-up is where Helios diverges from “another big GPU rack.”

UALink is the open consortium standard (AMD, Broadcom, Google, Meta, Microsoft, Intel, and dozens more — not NVIDIA). Spec ambition includes large pods and load/store semantics that Ethernet alone does not give you. UALink 2.0 landed in April 2026 with in-network compute language. Commercial native UALink switch silicon from Astera Labs and peers was still not at production scale as of early September 2026.

So Helios ships UALoE: run the UALink protocol over a standard 800 GbE physical layer and merchant Ethernet switch ASICs. AMD’s networking blog describes a single-hop fabric — every GPU reaches every other GPU through one switch — with up to 260 TB/s aggregate scale-up bandwidth and access to the full 31 TB of rack HBM in one domain. Resilience claims matter for people who actually run jobs: each GPU ties through 18 independent UALoE stations across switch trays so a link or tray event can fail over without killing the domain. vPods let you carve the 72-GPU domain into software-defined subsets for concurrent training and inference.

That is a coherent engineering story. It is also an admission: the open standard’s protocol is ready enough to put on Ethernet; the open standard’s switch silicon is not yet the thing you buy in volume for H2 2026 racks.

Why this pairs with NVHBM / Fusion

NVLink Fusion + NVHBM is the proprietary production path for custom XPUs that still want a proven 72-way domain: UCIe bridge chiplet into NVIDIA’s fabric, optional NVHBM base die for the memory path, NVIDIA keeping the switches and PHYs. Helios + UALoE is the open-protocol path that runs today on Ethernet bridging, with a roadmap toward native UALink switches later.

Hyperscalers are funding both. Alphabet sits on the UALink board, co-designs TPU v8i with MediaTek, and co-invested in the same MediaTek convertible-bond round that cemented MediaTek as NVIDIA’s NVLink Fusion XPU gateway. AWS is on the UALink board and named on Trainium4 + NVLink Fusion / NVHBM. That is not confusion. It is portfolio optionality at a scale most teams do not have.

For everyone else, the decision collapses to time vs replaceability:

• Need a custom XPU in a validated scale-up domain in 2026 / early 2027 → Fusion (and possibly NVHBM) is the shipping integration story.
• Willing to take an Ethernet-bridged UALink domain now and wait for native switch silicon → Helios / UALoE is the open bet, with Azure-class customers already on the deployment path per contemporary coverage.

Do not pretend those are the same product. Matching NVLink’s per-GPU 1.8 TB/s bidirectional figure on a slide is not the same as matching five generations of NVSwitch operational muscle.

Linux and ops caveats

On August 31, AMD posted v2 of the UALink mainline patches — on the order of 95 patches for infrastructure, plus a follow-on documentation series — wired toward AMDGPU and Helios UALoE. Fixes included 32-bit builds; AMD dropped a sysfs configuration API in favor of out-of-band tooling for now. Phoronix’s read: too late for Linux v7.3, plausible for v7.4; near-term Helios boxes will lean on vendor-blessed kernels.

That is normal for a new fabric. It is also a reminder that “open” does not mean “already boring in your distro.” Plan AFM / AFOS / fabric telemetry as first-class ops surface area, not as optional dashboards.

Other caveats I would put on any Helios capacity plan:

1. Vendor peaks and modeled tokens/$ are not field benches. Use them to size envelopes; validate with your own ISL/OSL mix before you bet a floor.
2. UALoE is a bridge. Ask AMD (and your NIC/switch vendors) for the migration story to native UALink switch ASICs — power, latency, and whether the software domain stays stable across that cutover.
3. ROCm migration cost is real. Halo Station and Helios both assume you can live outside CUDA. Budget porting and kernel maturity explicitly.
4. Not Halo Station. The deskside Threadripper Halo box and this 72-GPU rack share a brand family, not a deployment model.

Bottom line

Helios is AMD putting a full rack number on the table — 432 GB HBM4 per MI455X, 31 TB and 260 TB/s scale-up at the rack — and admitting the open interconnect ships first as Ethernet carrying UALink, not as native UALink silicon. Next to NVHBM and NVLink Fusion, that is the cleanest systems framing available in early September 2026: proprietary production-ready fabric with a memory-base-die lock-in path on one side; open protocol on merchant Ethernet with a silicon lag on the other.

If you run clusters, write the interconnect choice into the BOM the same way you write HBM generation into it. The GPU logo is loud. The switch tray decides who you can replace in five years.

Create-only. Specs above are from AMD’s July Helios materials, Hot Chips MI455X coverage, the Aug 31 Linux patch series, and early-September interconnect analysis; update when independent rack suites or native UALink switch SKUs publish.

Anpoo Sivanadi, Staff Software Engineer