Credo Weaver: HBM4-Class Edge Bandwidth at ~25× Capacity — OmniConnect VSR, No CoWoS

This morning’s Lightning V2 on Tenstorrent note was on-prem TTS economics on Blackhole. Last night’s Olmo-core 3 was a training-systems ticket. Yesterday morning’s Everspin CXL PERSYST was persistent media. Inference fleets still hit a different wall: decode is memory-bound and HBM beachfront is finite. On October 2, 2026, Credo published a technical post on OmniConnect and the Weaver memory fanout gearbox that claims HBM4-class die-edge bandwidth at roughly 25× the capacity — on organic substrate, without CoWoS.

Primary: Credo Oct 2 blog · Weaver product · OmniConnect · Weaver brief PDF · OCP LSI contribution (Aug 10, 2026). Numbers below are Credo’s unless noted. Treat HBM4 comparisons, beachfront densities, and hybrid leftover-edge examples as vendor architecture claims under the stated configs.

Spec sheet (named numbers)

That is a different purchase sentence from “another CXL pool” or “move the HBM controller into the stack.” This one is: can I attach LPDDR over a short serial beachfront and keep HBM4-class edge bandwidth without advanced packaging — and what does Credo claim when they try.

Why decode makes the wall visible

Prefill is mostly compute-bound. Decode flips it: each new token pulls a growing KV cache; only a fraction of the cores stay fed. Credo puts the compounding gap in plain numbers — compute ~3× every two years, memory bandwidth closer to 1.6× over the same window — and sketches serving-instance memory from roughly 0.4 TB (2020 dense) to about 1.2 TB (2023 MoE) toward ~5 TB for 2026 agentic workloads (~12× in six years), with KV catching up to weights. MoE residency, long context, and reasoning-token volume all push capacity and bandwidth at once.

Physics Credo is arguing against

Substrate area. Side-by-side LPDDR on a typical 100 mm × 100 mm organic tops out around 256 GB in their framing. HBM4 stacks buy peak bandwidth, not multi-terabyte capacity.

Beachfront. Parallel LPDDR5X at ~0.18 TB/s/mm and GDDR7 at ~0.4 lose to HBM4 at ~2.0 TB/s/mm. Packaging does not grow the perimeter. Once the edge is full, it is full.

OmniConnect’s answer: stop assuming memory must sit immediately beside the die. Serialize the link, keep FLIT / FEC / credit flow (drop speed-hopping / renegotiation), and let memory live out to ~250 mm. Fewer pins → roughly 10× die-edge density vs parallel LPDDR in their claim. The cost is latency — blog ~50 ns RTT with FEC; product sheet 40 ns — still a different class from rack CXL, but not free SRAM.

Weaver vs HBM4 — and beside it

The Oct 2 comparison that matters for a BOM conversation:

• Die-edge bandwidth: Weaver 6.4 TB/s vs HBM4 6.1 TB/s (OCP Aug release rounds to ~5% more BW).
• Capacity: 4.8 TB vs 192 GB HBM4 (~25×) on organic — no interposer, no CoWoS.
• Product-sheet maxima sit higher (16 TB/s / 6.4 TB); treat those as aggregate / multi-edge caps and keep the 6.4 / 4.8 vs HBM4 pair as today’s named bake-off.

Credo does not pitch a forced HBM replacement. Their hybrid example leaves ~10 mm of unused edge on a two-reticle / eight-HBM4 package (288 GB / 22 TB/s) and fills it with Weaver-connected LPDDR6 for +1.5 TB / 3.7 TB/s → 1.8 TB / 25.7 TB/s combined. They also argue sustained BW vs peak: spill HBM → LPDDR and sustained BW drops ~10×; spill to CXL and ~100×. A single-hop Weaver pool is their flatter-curve claim for long-context decode — architecture thesis until independent traces land.

Where it sits next to other boards

Do not collapse this into “Credo replaces HBM.” The claim is narrower: serialize the beachfront, match ~HBM4 die-edge bandwidth, unlock multi-terabyte LPDDR without CoWoS, optionally fill leftover edge beside HBM, and late-bind DRAM like DIMMs instead of welding capacity at tape-out.

Caveats

1. Vendor architecture claims. Bandwidth, capacity, beachfront, hybrid leftover-edge, and sustained-vs-tiered curves are Credo’s. Independent XPU bring-ups are not this post.
2. Blog vs product-sheet deltas. Oct 2 blog: ~50 ns / ~0.75 pJ/bit PHY and the 6.4 / 4.8 vs HBM4 pair; product page: 40 ns / 1.15 pJ/bit I/O and up to 16 TB/s / 6.4 TB. Quote the source next to the number.
3. Weaver availability. Unveil targeted 2H 2026 for the gearbox; 112G VSR for design-in. Confirm sampling before a frozen BOM.
4. Not a CXL pool, not NVHBM. Near-package VSR fanout ≠ rack CXL or Leo X / Inferra KV offload; NVHBM moves the controller into the HBM stack — same wall, different layer.
5. OCP is a contribution path. Aug 10, 2026 LSI Workstream + intended AXI framer — not a finished multi-vendor ecosystem. Product sheet is LPDDR5X; hybrid example uses LPDDR6 — verify when LPDDR6 PHYs ship.

How I would evaluate

1. Read the Oct 2 beachfront and hybrid leftover-edge sections next to the Weaver parameter table before quoting 25× or 6.4 TB/s.
2. Ask for a package diagram with your die-edge budget after HBM, and what Weaver lane count fits.
3. Time a decode-heavy long-context / agent workload sized to force HBM spill on your current tier — that is the cliff Credo is selling against.
4. Price late-bound LPDDR serviceability vs welded HBM yield separately from peak FLOPs.
5. Track the OCP LSI Workstream for third-party AXI implementations. Keep this board separate from Lightning TTS, Olmo-core training, Everspin CXL MRAM, and Leo X / Inferra — this is near-package memory fanout math.

Bottom line

On October 2, 2026, Credo put a clear systems claim on OmniConnect and Weaver: serialize the memory beachfront with 112G VSR SerDes out to ~250 mm, keep a stripped FLIT/FEC/credit path, and match HBM4 die-edge bandwidth (6.4 TB/s vs 6.1 TB/s) at roughly 25× the capacity (4.8 TB vs 192 GB) on organic packaging without CoWoS — with an optional leftover-edge hybrid that adds 1.5 TB / 3.7 TB/s beside eight HBM4 stacks. Product-sheet caps go to 16 TB/s / 6.4 TB at 40 ns RTT and 1.15 pJ/bit I/O on LPDDR5X. The Aug 10, 2026 OCP LSI Workstream puts the AXI framer on an open path. Treat the sustained-BW cliff argument and LPDDR6 migration as vendor thesis until independent bring-ups show up; the durable ticket is whether leftover die edge and late-bound LPDDR can buy multi-terabyte decode capacity without waiting on another HBM generation.

Create-only. Specs from Credo’s October 2, 2026 OmniConnect technical post, Weaver / OmniConnect product pages and PDF brief, and the August 10, 2026 OCP LSI contribution announcement. Update when third-party package bring-ups, LPDDR6 Weaver SKUs, or multi-vendor LSI implementations ship.

Sources: Credo Oct 2 blog · Weaver · OmniConnect · Weaver PDF · OCP LSI Aug 10, 2026.

Anpoo Sivanadi, Staff Software Engineer