Last week I wrote Helios UALoE as the open scale-up bridge and NVHBM as the Fusion-side memory lock-in. Tonight is the other Fusion story: decode silicon that wants the same rack you already buy for Vera Rubin.
On September 10, 2026, d-Matrix announced it will put next-gen Raptor XPUs into NVIDIA NVLink Fusion and the MGX rack reference architecture — Vera CPUs, NVLink switches, BlueField-4 DPUs, ConnectX-9 SuperNICs, Spectrum-X Ethernet, modular cable-free trays. Same day, NVIDIA’s blog frames the same deal as XPUs plugging into a liquid-cooled AI-factory path next to Vera Rubin NVL72 and, notably, Groq 3 LPX. That is the interesting systems sentence: two SRAM-ish decode bets, one proprietary fabric, one rack family.
Primary sources: d-Matrix PR, NVIDIA blog, The Register (Tobias Mann).
Spec sheet (named numbers)
| Announcement | Sep 10, 2026 — d-Matrix × NVIDIA NVLink Fusion / MGX collaboration (multi-year roadmap) |
| Product | Raptor XPU — follow-on to production Corsair; 3D DRAM + SRAM compute “two-story” package |
| Fabric / rack | NVLink Fusion scale-up; MGX rack ref; Vera CPUs; NVLink switches; BlueField-4; ConnectX-9; Spectrum-X |
| Connectivity partner | Astera Labs (NVLink Fusion ecosystem) |
| Workload split (vendor) | GPUs (e.g. Vera Rubin) for prefill; Raptor for decode; coding assistants / real-time chat / voice as latency targets |
| Tape-out / ship | Raptor tape-out before end of 2026; initial Raptor-in-MGX availability Q4 2027 (d-Matrix) |
| Patents / eval | >100 patents; evaluating at hyperscalers / frontier labs (vendor) |
| Hot Chips card (Register) | ~32 GB 3D-stacked DRAM @ 100 TB/s (~4.5× Rubin GPU memory bandwidth) |
| NVL144 XPU SKU (Register) | ~half card: ~16 GB 3D-DRAM, ~50 TB/s; 144 XPUs → ~2.3 TB capacity, ~7.2 PB/s peak aggregate BW |
| Capacity framing (Register) | ~2.3 TB ≈ models >4T parameters at 4-bit |
| Groq contrast (Register math) | Groq SRAM ~150 TB/s/chip but ~500 MB; trillion-param @ 8-bit might need >2,000 Groq 3 LPUs vs ~64 d-Matrix systems @ 8-bit / ~32 @ 4-bit |
The PR is the deployment contract. The Register table is the bandwidth arithmetic from Hot Chips — attribute it that way until d-Matrix publishes a formal datasheet.
What actually shipped today
Nothing you can rack in Q4 2026. What shipped is a path: Raptor designed for Fusion/MGX from the ground up, tape-out this year, MGX-integrated systems targeted Q4 2027. Sid Sheth’s line in the NVIDIA blog is the honest constraint set — capital, time, and energy are finite — and the bet is that borrowing NVIDIA’s liquid-cooled rack, fabric, and supply chain beats inventing a second one.
Heterogeneous disaggregation is the product story, not a footnote. Prefill stays on GPU compute (Vera Rubin class). Decode moves to Raptor’s memory-bandwidth-heavy package. That is the same phase split that makes Groq 3 LPX interesting next to Rubin, and the same reason I keep Jalapeño on a different axis (captive InferenceX scorecard, not a Fusion XPU tray).
d-Matrix also names Astera Labs for connectivity inside the Fusion ecosystem. That matters if you care who owns the PHY/bridge path when the XPU is not a GPU die.
How to read the Register bandwidth math
I am not treating Register’s NVL144 arithmetic as a BOM guarantee. I am treating it as the clearest public translation of Hot Chips into rack units:
- Card-class Raptor: 32 GB @ 100 TB/s — bandwidth closer to SRAM than to HBM stacks, with modest capacity per card versus HBM4 monsters.
- NVL144 XPU framing: ~half that card → 16 GB / 50 TB/s × 144 → ~2.3 TB and ~7.2 PB/s peak aggregate on one all-to-all NVLink fabric (Register: systems with up to 144 Raptors by end of next year).
- Capacity vs bandwidth trade: enough memory for multi-trillion-parameter models at 4-bit in Register’s framing, without pretending this is a training HBM envelope.
The Groq comparison in that article is useful as a chip-count intuition pump, not as my capacity plan. SRAM at ~150 TB/s with ~500 MB forces many dies per model; 3D DRAM at a fraction of that bandwidth with tens of GB per XPU shrinks the die count. Keep it labeled Register math. Your ISL/OSL mix and precision still decide the tray count.
Where this sits next to Helios, NVHBM, and LPX
| Lane | What you buy | Interconnect reality |
|---|---|---|
| NVHBM + Fusion | Custom XPU memory path into NVIDIA fabric | Proprietary production scale-up |
| Helios UALoE | 72× MI455X on open-protocol Ethernet bridge | UALink on 800 GbE until native switches |
| Groq 3 LPX | SRAM decode rack in the NVIDIA AI-factory story | NVIDIA-owned decode sibling |
| Raptor × Fusion | 3D-DRAM decode XPU on same MGX / NVLink family | Fusion peer list: Qualcomm, Arm, Marvell, Amazon, Fujitsu, MediaTek (Register); MediaTek/Marvell investment color ($3.5B / $2B) — no word if d-Matrix got similar |
Helios is “open protocol, Ethernet bridge, replaceability later.” Raptor is “specialized decode, but the switch tray and cooling plant are NVIDIA’s.” Those are not the same procurement risk. Fusion buys time-to-rack and a validated domain; it also writes NVIDIA into the BOM for Vera, NVSwitch, BlueField, ConnectX, and Spectrum-X even when the FLOPS logo says d-Matrix.
I would put Raptor next to LPX as two decode hypotheses under one fabric landlord, not as rivals that cancel each other. LPX is shipping-path SRAM density. Raptor is Hot Chips bandwidth with a Q4 2027 MGX availability date. If you already planned Fusion XPUs after NVHBM, this is the decode-shaped entry on that same whiteboard.
Caveats I would write into any Raptor capacity ticket
- Availability is Q4 2027 for MGX-integrated Raptor. Tape-out YE2026 ≠ production rack.
- 100 TB/s / 32 GB and the NVL144 aggregates are Register’s Hot Chips read, not a d-Matrix datasheet line item in the PR. Ask for the SKU that actually ships in the tray.
- Prefill/decode split is vendor architecture, not a measured InferenceX curve. Validate on your coding / chat / voice mix.
- Walled-garden economics. Register notes NVIDIA investment sweetners for other Fusion peers; d-Matrix terms are undisclosed. Price the full rack (Vera + switches + NICs + cooling), not the XPU alone.
- Not a substitute for Helios. Different fabric politics. Write the interconnect choice into the BOM the same way you write HBM generation into it.
- Not Jalapeño. Captive OpenAI ASIC vs merchant Fusion XPU — different buyer, different software surface.
Bottom line
d-Matrix’s Sep 10 announcement is the cleanest decode-XPU-on-NVLink-Fusion story in the Sep 8–10 window: Raptor’s 3D-DRAM package aimed at MGX next to Vera Rubin, with Register’s Hot Chips numbers (100 TB/s cards, NVL144 ~7.2 PB/s aggregate math) giving cluster readers something to argue about until a datasheet lands. Next to live Helios UALoE and Groq LPX, the decision is not “which logo is fastest.” It is whether you want open-protocol Ethernet bridging, SRAM decode under NVIDIA’s roof, or 3D-DRAM decode that still pays the Fusion tax for a proven switch tray.
If you run inference fleets, put Raptor on the same whiteboard as LPX and Helios with three columns: bandwidth per die, GB per die, and who owns the scale-up switch. The PR answers the third. Hot Chips (via Register) sketches the first two. Q4 2027 is when the sketch has to become a SKU.
Create-only. Specs above are from d-Matrix’s Sep 10 PR, NVIDIA’s same-day Fusion blog, and Tobias Mann’s Register Hot Chips translation; update when d-Matrix publishes a formal Raptor datasheet or independent rack suites.
Sources: d-Matrix · NVIDIA · The Register.
Anpoo Sivanadi, Staff Software Engineer