This morning’s Lightmatter Passage L20 CPX note was about how many fibers a 512-GPU optical scale-up pod actually needs. Tonight is the other half of the hyperscale inference ticket: what a captive GenAI ASIC looks like when HBM bandwidth, Softmax, and MoE FFN FLOPS are the design center — and the first TSMC samples just lit up.
On September 15–16, 2026, Bloomberg (via TrendForce and Mint) reported Meta is testing MTIA 450 (code name Arke), co-designed with Broadcom and fabbed at TSMC. Twelve dies arrived September 1; first silicon sat within 2–3% of simulation; day one they ran models from Meta, DeepSeek, and Alibaba. Mass deployment is aimed at 1H27, with a stated commit of more than 1 GW of the new chips over twelve months. Named package numbers live in Meta’s MTIA roadmap post (tables also in DCD and Fudzilla). Specs below are vendor/roadmap figures unless marked as Bloomberg bring-up color. Create-only; this is not a merchant SKU.
Spec sheet (MTIA 450 / Arke)
| Role | Captive GenAI inference ASIC (R&R + training as secondary) |
| Partners | Design: Meta + Broadcom; fab: TSMC (node undisclosed) |
| Module TDP | 1,400 W |
| HBM | 288 GB; 18.4 TB/s (2× MTIA 400’s 9.2 TB/s) |
| Compute | 7 PFLOPS FP8/MX8; ~21 PFLOPS MX4; 3.5 PFLOPS BF16 |
| Precision | 6× MX4 vs FP16/BF16; mixed low-precision without conversion tax |
| MoE / attention | +75% MX4 vs prior for MoE FFN; HW Softmax + FlashAttention |
| Scale-up | 72 devices; 1.2 TB/s scale-up; 100 GB/s scale-out |
| Software | PyTorch-native; vLLM plugin; torch.compile; Triton; OCP |
| Cadence | New chip ~every six months; reusable chassis/rack/network |
| Successor | MTIA 500 / Astrid — YE2027 entry; +50% HBM BW, up to +80% capacity, +43% MX4 |
| Availability | Internal only — not for sale; mass deploy early 2027 / 1H27 |
| Bring-up (Sep 2026) | 12 TSMC samples (Sep 1); 2–3% of sim; day-one Meta/DeepSeek/Alibaba; >1 GW / 12-mo |
Primary sources: Meta · TrendForce/Bloomberg · Mint · DCD · Fudzilla.
Why the HBM doubling is the real headline
Meta’s blog is blunt: for GenAI inference, HBM bandwidth is first-order, so MTIA 450’s job one is decode throughput, not another training-peak FLOPS slide. Doubling 9.2 → 18.4 TB/s at 288 GB is the same “move the memory wall” pressure I keep circling on NVHBM — except here the buyer is Meta’s own GW plan, not a Fusion partner.
Three moves sit next to that bandwidth. First, a 75% MX4 FLOPS bump aimed at MoE FFN, not dense pretraining. Second, Softmax / FlashAttention in hardware so attention stops competing for a general datapath — architecture intent until third-party long-context tables exist, but the right column if you care about interactive decode. Third, mixed low-precision without a conversion tax, plus custom data types; that is vendor language until you measure quality on your models.
The rack number that matters is continuity: 72 devices, 1.2 TB/s scale-up, 100 GB/s scale-out, same plant as MTIA 400 and 500. Meta’s velocity pitch is chiplet + rack reuse so a six-month silicon cadence does not force a facility rewrite. Bloomberg notes Meta canceled Olympus partly because even a ~30% chip-cost adder is hard to justify at gigawatt scale (Yee Jiun Song).
How this sits next to Jalapeño, Qualcomm×Amazon, and Rubin
OpenAI Jalapeño is Broadcom + TSMC inference silicon with a public InferenceX tokens-per-megawatt table and a not-for-sale rule. Qualcomm × Amazon is a multi-gen inference ASIC procurement line plus 1.6T optics. MTIA 450 is Meta’s third column: named HBM bandwidth, a 72-device domain, PyTorch/vLLM native software, and a Sep 1 bring-up that claims day-one DeepSeek and Alibaba — not only Meta’s own models.
It is not a substitute for Vera Rubin NVL72 or MI355X 512-GPU MLPerf rows. Those are (preview) serving results on merchant trays. MTIA 450’s public surface is still a roadmap table plus a Bloomberg bring-up anecdote. Meta’s “more efficient than whatever Nvidia is currently shipping” line does not belong in a capacity model without a matched workload, batch, and latency SLA.
Software is the quiet differentiator. A vLLM plugin that swaps FlashAttention and fused LayerNorm, plus a custom torch.compile backend, is how Meta argues frictionless adoption without a CUDA clone. The captive caveat remains: Meta’s kernels on Meta’s silicon inside Meta’s fleet — not a SKU you rack in colo tomorrow.
Caveats I would write into any MTIA capacity ticket
- Captive only. No buy path. Compare architecture lessons, not a purchase order.
- Vendor FLOPS and bandwidth. No independent InferenceX / AgentX / MLPerf closed division for Arke yet.
- Bring-up ≠ production. Twelve dies within 2–3% of sim is silicon health — not fleet yield, thermals, or RAS. Re-ask at 1H27 ramp.
- “Beats Nvidia” needs a matched column. Pin model, precision, batch, TTFT/TBT, and where the power meter sits.
- Inference-first. Do not import pretraining FLOPS intuition from Rubin trays.
- Same plant, new die. Scale-up stays 1.2 TB/s while HBM and MX4 climb — watch whether collectives become the next cliff.
- Astrid is still paper. MTIA 500’s higher BW/capacity/MX4 numbers are roadmap, not tape-out.
How I would use this tomorrow morning
Put MTIA 450’s 18.4 TB/s / 288 GB / 1,400 W row beside Jalapeño and Qualcomm × Amazon so the three hyperscaler ASIC bets share one spreadsheet. Treat the Sep 1 2–3%-of-sim bring-up as a silicon-health signal, not a serving bench. Keep Lightmatter fiber math on a separate tab — Meta’s scale-up domain is still a 72-device switched backplane story, not an Open CPX BiDi harness. If you buy GPUs for multi-tenant cloud, this is competitive intelligence. If you design an inference-first ASIC or a vLLM backend, the HBM-doubling + FlashAttention-in-silicon thesis is the part worth auditing against your own decode traces.
Create-only. Specs from Meta’s MTIA roadmap blog, DCD/Fudzilla tables, and Sep 15–16 Bloomberg bring-up reporting via TrendForce and Mint. Update when Meta publishes measured serving numbers or Astrid tapes out.
Sources: Meta AI blog · TrendForce · Mint · DCD · Fudzilla.
Anpoo Sivanadi, Staff Software Engineer