NewPhotonics NPG102 + Tower PH18DA: Laser-Integrated PICs Shipping for 800G–1.6T — and the CPX 6.4T On-Ramp

My Lightmatter Passage L20 CPX note was about what BiDi near-package optics do to a 512-GPU fiber plant once Open CPX is on the table. This morning is the other half of that cabling story: who is actually shipping the laser-integrated photonic engines those modules need — and what rate, form factor, and MSA path they claim when the foundry says “high volume.”

On September 17, 2026, Tower Semiconductor and NewPhotonics announced high-volume shipment of laser-integrated, serviceable optical-engine PICs built on Tower’s PH18DA silicon photonics platform. Primary sources: the Tower press release, the GlobeNewswire mirror, Converge Digest’s Sep 17 read, and Semiconductor Today’s Sep 18 write-up. Specs below are vendor claims; treat “first on PH18DA” and roadmap dates as supplier language until OEMs publish BOM and bring-up data.

Spec sheet (named numbers)

CPX here is the same Open CPX MSA socket language as Passage L20: optics next to the host ASIC / switch / accelerator package, not a faceplate transceiver fighting the same real estate as power and cooling. The difference in this note is supply — a named PIC SKU and foundry platform crossing from production orders into volume delivery.

What “laser-integrated” changes on the BOM

A conventional optical engine often treats the laser as a separate assembly problem: attach, align, qualify, and inventory an external source (or an ELSFP tray) next to a silicon photonics die that only does the passive and electro-optic half of the job. Heterogeneous InP-on-SiPho puts lasers and SOAs on the same PIC as modulators and detectors. Tower and NewPhotonics argue that cuts discrete optical interfaces, manufacturing variability, and time-to-yield — the boring reasons a capacity planner cares about a foundry PR.

Three operational consequences matter more than the “first on PH18DA” label:

1. Serviceable NPO. The release repeatedly pairs “near-packaged” with socket pluggable and serviceable. That is the architectural compromise between permanent CPO attach (shortest electrical path, worst field-replace story) and faceplate pluggables (easy swap, longer SERDES). You want the OE next to the package for 200G-class lanes, and you still want to pull a failed engine without scrapping the switch or GPU tray.
2. One PIC across FRO/LRO/LPO and NPO. Shipping the same laser-integrated engine family into front-panel reduced-optics modules and socketed NPO is how a supplier amortizes PH18DA yield across two deployment modes. For a neocloud BOM, that is a second-source and spare-parts argument, not a marketing taxonomy.
3. 200G/lane today, 6.4T CPX tomorrow. NPG102 at 200G per lane for 800G–1.6T engines is the volume product. NPC505 at 6.4T under CPX-MSA in 1H27 is the scale-up socket story that sits on the same Open CPX whiteboard as Passage L20’s 6.4 Tbps directional claim. Do not collapse them: one is shipping; one is a dated volume plan.

Converge Digest’s useful context: in March they reported NewPhotonics had placed the first volume-production orders for 800G/1.6T PICs on PH18DA. Sep 17 is the step from order to shipment. That is a commercialization milestone, not a new architecture paper.

How this sits next to Lightmatter, Helios, and Cornelis

Lightmatter Passage L20 CPX is a module + BiDi fiber-plant story: 6.4 Tbps/direction, 32 lanes @ 212.5 Gbps PAM4, Open CPX Type 2, modeled 131k → 65k fibers on a 512-GPU pod. This NewPhotonics note does not reopen that BiDi arithmetic. It asks whether the PIC supply behind CPX-class NPO is real enough to put on a 2026–2027 interconnect BOM — NPG102 shipping, NPC505 CPX-MSA volume in 1H27.

Helios UALoE and the open scale-up networking lane (UALink / ESUN / Ethernet bridges) are about what protocol sits above the optics. Qualcomm × Amazon 1.6T optical was an earlier optical density foil on the inference side. Put NewPhotonics next to those as engine silicon and foundry, not as a substitute for UALink switch silicon or Lightmatter’s BiDi module math.

I would not read “energy-efficient” and “manufacturing consistency” in the PR as a substitute for pJ/bit or FIT rates. Those belong in OEM datasheets and bring-up reports after ECOC demos land.

Caveats I would write into any NPO supply ticket

1. Vendor “first” and “high volume.” Tower’s claim that NewPhotonics is first on PH18DA into high-volume production is a foundry partnership statement. Ask for monthly ship rates and customer OEMs before treating it as industry share.
2. 800G–1.6T ≠ 6.4T. NPG102 shipping rates are the lower-density engines. NPC505 6.4T is 1H27 planned volume — after Passage L20’s anticipated Q1 2027 EVK window on the Lightmatter side. Align calendars; do not assume concurrent availability.
3. Lane math differs. Lightmatter’s L20 foil uses 212.5 Gbps PAM4 on 32 lanes for 6.4 Tbps/dir. NewPhotonics’ shipping NPG102 is 200G/lane for 800G–1.6T; the NPC505 color Converge Digest cites is 224 Gbps PAM4 on a DR32 engine. Different products, different lane tables — do not mix them in one CapEx model.
4. MSA compliance is a socket claim. “CPX-MSA compliant” on NPC505 means the chipset targets the Open CPX mechanical/electrical envelope. It is not automatic interoperability with every Guide DR laser or every BiDi module on the MSA roster.
5. No published pJ/bit or reach table in the HVM PR. Passage L20’s product page claims ~5 pJ/bit and >500 m SMF; this Tower/NewPhotonics release does not put matching efficiency or reach numbers on NPG102. Hold those cells empty until OEM modules publish them.
6. ECOC is a demo, not a rack qualification. Sep 21–23 Malaga meetings are useful for samples and roadmap slides. They are not a substitute for hyperscaler optical bring-up on your switch ASIC.

How I would use this tomorrow morning

Put an NPG102 (shipping) / NPC505 6.4T CPX (1H27) row next to your Passage L20 CPX fiber model so engine supply and MSA socket timing sit beside BiDi fiber counts — not underneath them as a “optics will exist” assumption. If you are sizing FRO/LRO/LPO faceplate ports for scale-out while parking NPO for scale-up, ask whether one PH18DA-based PIC family can cover both spare pools. If you are already on NVLink Fusion or UALoE for the protocol layer, read this as optical-engine second-source intelligence for the CPX socket, not a reason to change the fabric.

Create-only. Specs and dates from Tower’s Sep 17 release, the GlobeNewswire mirror, Converge Digest’s Sep 17 commercialization note, and Semiconductor Today’s Sep 18 summary. Update when NewPhotonics or an OEM posts NPG102 pJ/bit / reach tables, or when NPC505 exits “planned 1H27 volume” into a dated ship notice.

Sources: Tower Semiconductor PR · GlobeNewswire · Converge Digest · Semiconductor Today.

Anpoo Sivanadi, Staff Software Engineer