This morning’s EPYC Venice vs Vera note was host-CPU SPECrate and Stream arithmetic. Last week’s Lightmatter Passage L20 CPX and Helios UALoE notes were the optical plant and the open Ethernet bridge when native UALink switch silicon is not volume-ready yet. This evening is the other half of that open scale-up ticket: who is sampling the fabric and the I/O chiplets that try to make “not NVLink” a real BOM line, with named Tbps, an 800 Gbps multimode NIC/switch family, and protocol-agnostic dies that claim more than double today’s accelerator interconnect caps.
At AI Infra Summit week (September 14–15, 2026), two announcements landed in the same lane. Cornelis Networks introduced Active Compute Fabric (ACF) — programmable compute inside scale-up and scale-out networking — alongside ~$205 million in funding and a Qualcomm Technologies rack-scale evaluation. Delos Data closed more than $100 million and expanded Nonstop AI with a multi-protocol Data Interface for heterogeneous agentic inference clusters. Primary sources: the Cornelis ACF press release, Network World’s Spelman interview, SiliconANGLE on ACF traffic reduction, The Register’s Cornelis + Delos write-up, the Delos funding PR, and Converge Digest’s Data Interface table. Bandwidth and utilization numbers below are vendor claims or modeled projections unless a third-party pod measurement is cited.
Spec sheet (named numbers)
| Cornelis | Delos | |
|---|---|---|
| Announcement | Sep 14, 2026 (ACF + funding + Qualcomm) | Sep 15, 2026 (funding + Data Interface) |
| Capital | ~$205M (IAG-led, per SiliconANGLE) | >$100M (Matrix, Playground, Socratic, Capricorn TIF, Matter, IAG, et al.) |
| Standards | Scale-up UALink / ESUN; scale-out Ultra Ethernet | Protocol-agnostic: ESUN, UALink, or other |
| Availability | CN5000 shipping; CN6000 800 Gbps multimode SuperNIC/switch sampling, broader Q4 2026 | Clusters on existing infra today; Nonstop AI Server samples end of 2026 |
| Wire modes (CN6000) | One ASIC: native Omni-Path or RoCEv2 Ethernet (Ethernet encapsulation keeps Omni-Path congestion/credit/spray internals) | N/A (endpoint I/O, not a switch SKU) |
| In-path work | Licensed RISC-V in NIC + switch; collectives (e.g. AllReduce), KV-cache assemble, MoE dispatch, MPI offload, checkpointing, gradient compression in transit | Hardware failure detect/recover; MoXI “Mixture of X” compose story |
| Headline BW | Product family 800 Gbps CN6000 | I/O die >30 Tbps (~8 TB/s bidirectional); NPO 10+ Tbps; card 400+ Gbps |
| Comparison claim | Model: ~50% GPU hours waiting in a 100,000-GPU system → ~$1.68B/yr idle @ $4/GPU-hour, 8,400 hrs/yr; pre-prod sims up to ~50% network traffic cut | Register: >30 Tbps die “more than double” Nvidia/AMD interconnect caps (~3.6 TB/s bidirectional) |
What “active” means when the fabric stops being a pipe
Cornelis’ argument is familiar if you have lived through SHARP-class collectives: a passive pipe makes every AllReduce, cache fetch, and expert dispatch cost accelerator time at both ends. SiliconANGLE quotes CMO Brandon Draeger: “The payload does not arrive the way it left.” Partial results combine inside the fabric; compressed gradients move as a fraction of original size; the work happens once on the path the bytes were already taking.
ACF packages that idea as an open baseline over UALink / ESUN and Ultra Ethernet, not a Cornelis-only proprietary scale-up link — the political sentence for accelerators outside NVLink Fusion. Network World adds the silicon detail for a BOM review: Cornelis licenses third-party RISC-V cores into NIC and switch ASICs rather than equating smart-NIC offload with KV-cache and MoE compute. Spelman’s utilization pitch is the economic twin of the Lightmatter fiber model — reclaim idle GPU hours — with the same caveat: vendor model until your workload is on the meter.
CN6000 is the near-term SKU you can ask about in a QBR. 800 Gbps multimode silicon that speaks Omni-Path or RoCEv2 Ethernet, with Ethernet mode still running Omni-Path-style congestion management inside the chip before retranslation. In Ethernet mode it can sit next to third-party switches (Broadcom Tomahawk called out). CN5000 ships today; CN6000 samples now with broader availability aimed at Q4 2026. Keep ACF roadmap features separate from the multimode NIC/switch you can actually PO.
What Delos adds that Cornelis does not
Delos attacks the endpoint ↔ network boundary, not a Cornelis-class switch line. Converge Digest’s three form factors:
- >30 Tbps multi-protocol I/O chiplet for GPUs / XPUs / accelerators (~8 TB/s bidirectional).
- 10+ Tbps near-packaged optics module pairing the interface with optical engines.
- 400+ Gbps card for CPUs, flash, and memory endpoints.
The Register’s comparison to ~3.6 TB/s bidirectional on current Nvidia/AMD accelerator interconnects is why this is a systems note: if those I/O dies land inside accelerator packages, the scale-up physical layer stops being “whatever the GPU vendor soldered.” Protocol agnosticism is the deliberate contrast to NVLink Fusion’s NVSwitch dependency — the same open-vs-walled tension Helios UALoE and d-Matrix Raptor on NVLink Fusion keep circling from opposite sides.
“Nonstop” is about agentic inference that keeps running through failures — link loss, missing accelerator, software-update disruption — with hardware-side detect/recover. Clusters run on existing infrastructure today; the Server samples late 2026; the Data Interface silicon remains co-design-bound (package integration is the long pole).
How this sits next to Lightmatter, Helios, Raptor, and Venice
- Lightmatter L20 CPX — fiber plant CapEx once scale-up is optical.
- Helios UALoE — open Ethernet bridging while purpose-built UALink switches are scarce.
- Raptor × NVLink Fusion — decode silicon inside Nvidia’s garden.
- EPYC Venice vs Vera — host-CPU SPECrate / Stream / rack.
- Cornelis + Delos — open fabric compute and protocol-agnostic I/O dies with named 800G and >30 Tbps figures.
Do not collapse them into one “networking is hot” slide. Optics plant, Ethernet bridge, Fusion decode, host CPU, and open fabric/I/O are five purchase and failure domains.
Caveats I would write into any open scale-up ticket
- Pre-production math. Cornelis’ 50% wait / $1.68B idle / ~50% traffic-cut figures are modeling and pre-prod sims. Re-run on your collective profile.
- Delos Tbps are design targets. >30 / 10+ / 400+ Gbps and “10× latency / efficiency” need a measured customer pod.
- I/O die = co-design. Delos wins only if a GPU/XPU vendor integrates the chiplet — not a faceplate SKU next quarter.
- CN6000 Ethernet is still Omni-Path inside. Verify congestion behavior under your leaf and ECMP.
- Open standards ≠ shipping UALink switches. Purpose-built UALink switches remain scarce; Helios’ bridge caveats still apply.
- Not a substitute for MLPerf rows. Does not change Vera Rubin or MI355X tokens/s — only what you wire between tokens.
- Funding ≠ availability. CN6000 Q4 2026 and Delos Server end-2026 are the calendar lines for a purchase plan.
How I would use this tomorrow morning
If you are quoting a non-NVLink (or mixed) rack-scale inference domain: (a) put CN6000 800G sampling / Q4 2026 next to your RoCE vs Omni-Path leaf strategy before freezing a SuperNIC SKU, (b) ask which accelerator vendors are in Delos I/O-die co-design rather than treating >30 Tbps as a catalog part, and (c) keep this column beside Lightmatter CPX, Helios UALoE, and Raptor Fusion. If your fleet is pure NVL72 copper inside the tray, this note is early; if UALink/ESUN is already in a 2027 rack RFP, the named 800G and >30 Tbps figures are the parts worth auditing first.
Create-only. Specs from Cornelis’ Sep 14 ACF / funding announcement and Network World / SiliconANGLE / Register coverage, plus Delos’ Sep 15 funding PR and Converge Digest’s Data Interface table. Update when CN6000 GA ships or a third-party board publishes a measured Delos I/O-die bring-up.
Sources: Cornelis PR · Network World · SiliconANGLE · The Register · Delos PR · Converge Digest.
Anpoo Sivanadi, Staff Software Engineer