EdgeCortix RAIDEN: 3.36 PFLOPS FP4 on Four Dies — Thick-Edge Physical AI as One Chiplet Stack

This morning’s WhiteFiber Continuum note was the campus purchase: what you do when GPUs cannot all live under one roof. Last night’s Claude Opus 5.5 note was a model purchase. Tonight is silicon again — a multi-die Physical AI chiplet for the thick edge, with named FP4 ceiling, memory capacity, die-to-die bandwidth, and chip-to-chip scale-out a board designer can put next to an Axelera Europa card or a SAKURA-II module.

On September 23, 2026, Japanese fabless EdgeCortix unveiled RAIDEN, a scalable AI chiplet platform built around the latest DNA-X accelerator architecture and the existing MERA software stack. Primary sources: the BusinessWire / FinancialContent launch, Semiconductor Digest’s same-day rewrite, and EdgeCortix’s product home. Numbers below are vendor architecture claims until samples land and third-party pods publish.

Spec sheet (named numbers)

RAIDEN is not “another edge NPU sticker” and not a datacenter HBM island. It is a claim that Physical AI at the thick edge — robots, aerospace/defense platforms, on-prem edge AI servers — needs compute, memory capacity, memory bandwidth, and connectivity to scale together under one software investment, from a single die inside a machine to a four-die package that still speaks MERA.

What the chiplet ladder is supposed to change

Most Physical AI teams I talk to still buy three incompatible boxes: a vision/inference card for perception, a general CPU/GPU for planning and agents, and a separate controller path for actuation. When the model grows or the product lifecycle outlasts the silicon generation, they re-partition the pipeline and rewrite the glue.

EdgeCortix’s pitch is the opposite: one DNA-X + MERA platform that scales die count instead of forking architecture. X1 for the machine-local node, X2 for mid-tier, X4 for the flagship that tries to keep perception, reasoning, application processing, and control on a tightly integrated four-die system rather than a bag of discrete accelerators. The PR is explicit that X4 is meant to operate as one AI system, not four isolated cards glued by PCIe.

That is a different CapEx sentence from Axelera Europa (shipping 629 TOPS / 45 W PCIe AIPU), Groq 3 LPX, or d-Matrix Raptor. Those are merchant cards for inference lanes you already own. RAIDEN argues for thick-edge packages you design into the product, with a software path that does not reset when you move from one die to four.

The bandwidth triangle worth checking

Three numbers on the X4 sheet matter more to me than the PFLOPS headline:

1. 548 GB/s memory bandwidth vs 256 GB capacity. Capacity is generous for thick-edge multimodal / agentic context; bandwidth is the constraint you will feel first under concurrent perception + reasoning. Ask how many independent memory channels sit behind that 548 GB/s, and what happens when four dies contend.
2. 1.54 TB/s aggregate die-to-die. That is the claim that four DNA-X dies behave as one fabric, not four cards. Ask topology (all-to-all vs mesh), latency, and whether MERA collectives use that path natively.
3. 6.4 Tb/s chip-to-chip scale-out. Package-to-package escape when one X4 is not enough. Convert carefully: 6.4 Tb/s is 0.8 TB/s unidirectional if you treat it as bit/s / 8 — still serious for thick-edge scale-out, but a different order of magnitude from Continuum’s campus fabric. Ask media (SerDes generation, reach, cable vs board), and whether Unigen’s server platforms expose it as a product feature or a lab demo.

DNA-X’s micro-code programmable matrix and vector engines are the software half of that triangle. EdgeCortix says Physical AI is more than neural-network inference — perception, reasoning, application processing, and control need to co-reside. Runtime reconfigurability from earlier DNA generations stays; micro-code is the new lever for non-standard kernels without bolting on a second SoC. MERA is the continuity bet: work on SAKURA-II today is supposed to carry forward, and X1→X2→X4 should not force a new compile toolchain.

Where it sits next to Europa, Continuum, and the GPU island notes

Five purchase domains. RAIDEN does not move KV across a metro and does not replace an NVL72. It answers the product question Continuum and Europa leave open: when the AI has to live next to the machine for years, do you redesign the board every generation, or do you buy a chiplet ladder that scales under one software stack?

Caveats for a RAIDEN ticket

1. Samples early 2027 / volume H2 2027 — design-in story, not a Continuum-style “available yesterday” SKU.
2. X1 and X2 specs still withheld — you cannot size the low/mid rungs from the public sheet yet.
3. No public TDP / tokens-per-watt table — measure before comparing to Europa’s 45 W or a GPU card.
4. 3.36 PFLOPS is FP4 peak architecture — ask precision mix, sustained fraction, and whether FP8/INT8 rows exist.
5. 548 GB/s vs 256 GB — capacity-heavy vs datacenter HBM islands; validate concurrent multimodal + agent loads.
6. Kawasaki / Unigen are design wins, not published pod results — ask schedule, form factor, and which config each uses.
7. MERA continuity is a claim — port a SAKURA-II model through Early Access before believing “no rewrite.”
8. Do not confuse with killed Huawei Atlas / Ascend SuperPoD numbers. That lane stays closed here.

How I would evaluate if I ran thick-edge systems

1. Early Access schedule + first X1/X2 public sheets — without them the ladder is a flagship slide.
2. Port one perception + planning + control pipeline from SAKURA-II and measure the MERA migration delta.
3. Stress the 1.54 TB/s die-to-die path with a multi-die collective that mirrors your agentic batch.
4. Memory bandwidth headroom at 256 GB residency under concurrent vision + LLM context.
5. Unigen server SKU timeline — is 6.4 Tb/s chip-to-chip a product connector or a roadmap checkbox?
6. Power: W/die and W/package at the configurable settings you would actually ship.

Thick-edge ticket read

RAIDEN is the densest named Physical AI chiplet sheet after Continuum ate the morning networking slot. Shipping PCIe inference lanes stay on Europa. Multi-year machines or on-prem edge AI servers that must climb 1→4 dies without rewriting MERA should put RAIDEN Early Access on the calendar, demand the missing X1/X2 rows and a real TDP table, and treat 3.36 PFLOPS / 256 GB / 1.54 TB/s / 6.4 Tb/s as architecture targets to verify on early-2027 samples — not fleet assumptions today.

Create-only. Specs and dates from EdgeCortix’s Sep 23 RAIDEN launch, BusinessWire / FinancialContent, Semiconductor Digest’s same-day rewrite, and EdgeCortix’s product home. Compute, memory, die-to-die, and chip-to-chip numbers are vendor architecture claims until samples land and a named third-party pod publishes. Update when X1/X2 sheets or a TDP table ship, or when Early Access reproduces a SAKURA-II pipeline on RAIDEN.

Sources: BusinessWire / FinancialContent · Semiconductor Digest · EdgeCortix.

Anpoo Sivanadi, Staff Software Engineer