PicoJool’s 200G GaAs VCSEL: >37 GHz, Three Paths to 1.6T, and the Unconstrained-Supply Bet

This morning’s Supermicro Vera Rubin NVL72 shipping note answered the rack purchase: can you order the cold-plate-to-tower coherent domain. WhiteFiber Continuum answered the campus purchase: second site when one hall hits the power wall. Tonight is the laser purchase underneath short-reach scale-up AOCs and near-packaged optics.

On September 24, 2026, PicoJool said it closed a $27.5 million Series A led by Socratic Partners, with Hudson River Trading participating, bringing total funding to $39.5 million after a $12 million Playground Global seed. The money is framed as execution: qualify, manufacture, and move chip-level VCSELs and microVCSELs into AOC and NPO modules — not invent a new physics paper.

Primary sources: PicoJool’s Series A release, the June 200G VCSEL product announcement, SiliconANGLE’s Sep 24 write-up, and the July ChipStrat interview with CEO Al Yuen for roadmap color. Numbers below are vendor claims until your own link qualification tickets publish measured BER, power per bit, and yield.

Spec sheet (named numbers)

That is a different CapEx sentence from NewPhotonics NPG102 + Tower (laser-integrated PICs shipping into 800G–1.6T engines) or Lightmatter Passage L20 CPX (BiDi NPO that halves a fiber plant). Those posts are engines and packaging. PicoJool is the emitter bet: will short-reach scale-up stay on multi-mode GaAs VCSELs that already ship in the millions, or migrate to InP / silicon-photonics lanes that were built for longer reach and thinner volume?

What “200G per lane” is supposed to buy

Copper at 200G/lane is collapsing to a few meters of useful reach inside a hot GPU row. Hyperscale training and agentic inference treat thousands of accelerators as one machine, so the interconnect BER bar moved from classic Ethernet comfort (~10⁻⁶) toward error-free territory (10⁻¹⁰–10⁻¹²). That is why expensive single-mode solutions walked into the hall: they already lived at low BER. PicoJool’s claim is the pragmatic counter — raise the VCSEL bar to 200G, keep the GaAs fab line that already knows millions-per-month, and offer three recipes to the same 1.6T aggregate depending on power and BER taste.

1. 8×200 PAM4 — “fast and narrow,” closest to a straight electrical-to-optical map, more DSP / integrity cost.
2. 16×100 LPO — run a 200G-capable die at half rate for cleaner noise; linear-drive / low-power path.
3. 32×50 NRZ microVCSEL — “slow and wide,” full 0/1 SNR, many lanes, aimed at OCI-class and very low BER budgets.

The Sep 24 release also calls out 50G NRZ microVCSEL interest for optical compute interconnects and 64G NRZ/PAM4 for PCIe 6.0-based NPO. That is how this sheet sits next to fabric-attached memory and KV work like Astera Leo X: different layers, same question of how bits leave the tray without melting the power budget.

The manufacturing asterisk that is the whole thesis

Yuen’s ChipStrat argument is not “VCSELs are new.” It is that GaAs VCSEL capacity is unconstrained relative to indium phosphide substrate and packaging lines sized for metro/long-haul volumes. WIN is the named wafer partner; PicoJool designs epi and device, WIN processes, module partners build AOCs/transceivers. Cycle-time color from the interview: roughly 8–10 weeks for VCSEL wafers, then packaging weeks on top — limited by build time, not by “sold out through next year” InP scarcity, if you believe the unconstrained claim.

That is the purchase checklist item, not the Series A headline. Ask for:

1. Known-good-die yield on the 200G process at WIN under your temp/bias quals.
2. BER vs reach vs fiber plant (OM3/OM4/OM5 assumptions) at the 8×200 / 16×100 / 32×50 operating points you actually want.
3. Module partner and SKU — chip sampling ≠ AOC on a PO; which integrator owns the connector, driver, and reliability log.
4. Tier-1 qualification clock — ChipStrat: small customers ~3 months, tier-1 often >6 months; early-2027 volume is a ramp start, not guaranteed hyperscaler GA.

Where it sits next to Continuum, NewPhotonics, and Lightmatter

Five related tickets. PicoJool does not replace Continuum’s campus math or NewPhotonics’ PIC sheet. It answers whether the emitter under your next AOC/NPO generation stays on a volume GaAs line that already knows consumer-scale wafers.

Caveats for a PicoJool ticket this week

1. Series A is not a shipping PLU. Early sampling + early-2027 volume is the honest timeline; treat 2026 as qualification, not hall cutover.
2. >37 GHz and 200G/lane are vendor device claims — demand measured eye / BER under your fiber and temperature.
3. Three 1.6T recipes are not three fielded SKUs. Confirm which module partners sample which flavor.
4. “Unconstrained” GaAs is a capacity thesis vs InP — verify lead times and wafer allocation in writing; do not paste ChipStrat wafer math into a CapEx sheet without a quote.
5. Roadmap color to 3.2T / 12.8T (bi-di second wavelength, 2-D arrays, 100G NRZ) is interview roadmap, not a Sep 24 datasheet.
6. Do not confuse with killed Huawei Atlas / Ascend SuperPoD / Hi-ONE NPO amplification. That lane stays closed here.
7. Not a rematch of Continuum. Continuum is fabric + WEKA across 83 km; PicoJool is the laser diode inside short-reach links.

How I would evaluate if I ran the hall

1. Pick the 1.6T recipe that matches your power/BER budget (8×200 vs 16×100 LPO vs 32×50 NRZ) before you argue “VCSEL vs SiPh.”
2. Get a written sampling matrix: chip vs AOC vs NPO, partner name, OM fiber class, target BER, and qualification plan through early 2027.
3. Ask WIN/PicoJool for yield and cycle-time commitments at the volume you would actually pull — not the theoretical wafers-per-week ceiling.
4. Put the same reach/power test next to whatever PIC / CPO path you already track from NewPhotonics or Lightmatter; keep the layers separate.
5. Budget the Series A story as funding to finish quals, not as proof the die already won the row.

If you are buying short-reach scale-up optics for the next GPU generation, the useful question is no longer “can VCSELs do 200G in a press release.” It is whether PicoJool’s GaAs line, WIN partnership, and three 1.6T recipes survive your BER and reliability gates before copper runs out of meters inside the rack.

Create-only. Specs and dates from PicoJool’s Sep 24 Series A release, the June 200G VCSEL product announcement, SiliconANGLE’s Sep 24 write-up, the July ChipStrat interview with CEO Al Yuen, and Electronics Weekly’s June sampling note. Bandwidth, volume, and capacity numbers are vendor claims until your own BER, power-per-bit, and yield tickets publish.

Sources: PicoJool Series A · 200G product page · SiliconANGLE · ChipStrat / Al Yuen · Electronics Weekly (June sampling).

Anpoo Sivanadi, Staff Software Engineer