The live Vera Rubin NVL72 MLPerf note answered the benchmark purchase: what does one rack do on Qwen3-VL, and what is the AgentX tokens-per-megawatt asterisk. This morning is the ops purchase. On September 23, 2026, Supermicro said it is now shipping NVIDIA Vera Rubin NVL72 racks integrated with its Data Center Building Block Solutions (DCBBS) and DLC-2 direct liquid-cooling stack — cold plates through manifolds to cooling towers, not a GPU tray and a promise.
Primary sources: the PR Newswire shipping release, Supermicro’s same-day press page, and the Vera Rubin NVL72 datasheet PDF. Numbers below are vendor claims until your own L11/L12 tickets and third-party pods publish. Where the PR and datasheet disagree, I call it out.
Spec sheet (named numbers)
| Product | Supermicro NVIDIA Vera Rubin NVL72 rack-scale AI |
| Status | Now shipping (Supermicro, Sep 23, 2026) |
| Per rack GPUs / CPUs | 72 NVIDIA Rubin GPUs + 36 NVIDIA Vera CPUs |
| Compute trays | 18× 1U trays — 4 Rubin + 2 Vera each |
| HBM4 per GPU (claimed) | Up to 288 GB |
| HBM4 per rack (claimed) | 20.7 TB total |
| Aggregate HBM4 BW / rack (datasheet) | 1.6 PB/s |
| Host / context memory / rack (claimed) | Up to 54 TB LPDDR5X (SOCAMM) |
| NVLink scale-up / rack | Datasheet: 260 TB/s via 9 sixth-gen NVLink switch trays; PR text said 216 TB/s — ask which figure is current on the SKU you order |
| Per-GPU NVLink (datasheet) | 3.6 TB/s bidirectional |
| Scale-out / GPU (datasheet) | Up to 1.6 Tb/s via 4× ConnectX-9 SuperNICs per tray (Spectrum-X Ethernet or Quantum-X800 InfiniBand) |
| North-south / tray (datasheet) | BlueField-4 DPU, up to 800 Gb/s |
| Power shelves (datasheet) | 4× 3U 110 kW |
| Cooling | DLC-2 stack; in-row CDU up to 2.2 MW (datasheet) with N+1 pumps — PR quoted 1.8 MW per CDU |
| Optional residual heat | Rear-door heat exchanger; Liquid-to-Air sidecar CDU (200 / 500 kW options on datasheet) |
| Scalable Unit (PR) | 16 compute racks → 1,152 Rubin GPUs + 331 TB HBM4, with balanced cooling, power, storage, context memory, networking |
| Blueprint envelope (PR) | Balanced BOM from 5 MW to gigawatt scale |
| Integration path | Site survey → design → integration → L11 / L12 test → on-site deploy → ongoing support |
That is a different CapEx sentence from WhiteFiber Continuum (second campus over metro fiber) or Axelera Europa (shipping 45 W PCIe AIPU). Continuum answers where else can the GPUs live. Europa answers what efficient card do I put in an existing chassis. This NVL72 shipping note answers can I order the 72-GPU coherent domain, the liquid loop, and a 16-rack Scalable Unit BOM from one accountable team today.
What “shipping” is supposed to change
Most Vera Rubin conversations I still hear are slideware: MLPerf rows, HBM4 stack counts, NVLink gen numbers, and a vague “2H26/4Q” availability hedge. Supermicro’s claim is narrower and more useful for anyone who runs clusters: the rack is orderable, the liquid path is productized (cold plate → manifold → CDU → tower), and the Scalable Unit is a named 16-rack building block rather than “buy N racks and figure out the facility later.”
The datasheet frames the rack as one coherent NVLink domain, not 72 PCIe cards that happen to share a chassis. Eighteen compute trays and nine sixth-gen NVLink switch trays are the mechanical expression of that claim. Scale-out escapes the domain over ConnectX-9 at up to 1.6 Tb/s per GPU, with BlueField-4 for the north-south path. If you already operate Spectrum-X or Quantum-X800 fabrics, that is the integration sentence that matters more than another FLOPS headline.
Charles Liang’s quote in the PR is marketing, but the operational claim underneath it is testable: every layer between cold plate and cooling tower is supposed to come from the same DCBBS portfolio, and every rack is supposed to ship validated with that full liquid stack. That is how you compress time-to-online when the heat load no longer fits air.
The three numbers to check before you sign a Scalable Unit
- 20.7 TB HBM4 and 1.6 PB/s aggregate. Capacity is the residency story for long-context / multi-agent batches; bandwidth is what you feel when all 72 GPUs hammer HBM together. Ask how Supermicro and NVIDIA want you to measure sustained fraction under your mixture of training and agentic decode, not only datasheet peak.
- 260 TB/s vs 216 TB/s NVLink scale-up. The datasheet and PR disagree. Treat that as a purchase checklist item: which figure is on the SRS-VR-NVL72 revision you are buying, and what is the per-GPU 3.6 TB/s bidirectional path under contention.
- 1.8 MW vs 2.2 MW CDU and the 16-rack Scalable Unit. Cooling is the real schedule risk. Ask which CDU SKU ships with your Blueprint, what N+1 means for your hall, and whether the 331 TB / 1,152 GPU Scalable Unit BOM includes context-memory storage and fabric oversubscription assumptions you can live with.
Secondary but real: up to 54 TB LPDDR5X on the Vera CPUs is a host/context pool next to HBM4, not a substitute for it. Pair that mentally with fabric-attached KV work like Astera Leo X and orchestration like Lightbits Inferra — different layers, same question of where tokens live when HBM is full.
Where it sits next to Continuum, MI355X, and the live MLPerf note
| Purchase | Product | What it buys |
|---|---|---|
| Benchmark / AgentX asterisk | Vera Rubin NVL72 MLPerf | What one rack did on the public suite |
| Orderable rack + liquid BOM | Supermicro Vera Rubin NVL72 shipping | Cold-plate-to-tower path and 16-rack Scalable Unit |
| Cross-campus scale-across | WhiteFiber Continuum | Second site when one campus hits power/space |
| Merchant GPU island (AMD) | MI355X MLPerf | Alternate HBM island math at 512-GPU scale |
| CPU next to the island | EPYC Venice vs Vera | Host SPECrate / Stream context |
| Decode add-in on MGX family | d-Matrix Raptor | NVLink Fusion decode beside the GPU domain |
Five related purchases. Shipping NVL72 does not replace Continuum, and it does not retire the MLPerf asterisk. It answers the question the benchmark post cannot: is the liquid-cooled coherent domain a purchase order yet, or still a roadmap slide?
Caveats for a Vera Rubin ticket this week
- “Now shipping” is a vendor claim — ask lead time, allocation, and which Blueprint power envelope you actually get on the first PO.
- PR vs datasheet deltas on NVLink aggregate (216 vs 260 TB/s) and CDU rating (1.8 vs 2.2 MW) — resolve in writing before facilities designs freeze.
- Up to 10× per-watt vs Blackwell on the datasheet is a vendor target, not a measured column in this post; keep that separate from the live MLPerf numbers.
- L11/L12 testing is named — ask what those gates cover for your fabric choice (Spectrum-X vs Quantum-X800) and residual heat path (rear door vs L2A sidecar).
- Scalable Unit storage and context memory are mentioned without a public SKU table here — pull the full BOM, not only GPU count.
- Do not confuse with killed Huawei Atlas / Ascend SuperPoD numbers. That lane stays closed on this site.
- EdgeCortix RAIDEN remains a separate thick-edge chiplet story from the Sep 24 package — different purchase domain; do not merge the tickets.
How I would evaluate if I ran the hall
- Get the SRS-VR-NVL72 revision and the DCBBS Blueprint PDF for the MW envelope you can actually feed.
- Resolve the 216 vs 260 TB/s and 1.8 vs 2.2 MW deltas with the account team in one email thread.
- Run a short L12 acceptance that includes NVLink domain collectives and Spectrum-X / Quantum-X800 escape under your real oversubscription.
- Measure HBM residency vs the 54 TB LPDDR5X host pool on one long-context agentic workload before you buy the 16-rack story.
- Keep the MLPerf post as the performance asterisk and this shipping note as the deployment asterisk — both required, neither sufficient alone.
If you are buying Vera Rubin this quarter, the useful question is no longer “does the architecture slide look good.” It is whether Supermicro’s cold-plate-to-tower stack and 16-rack Scalable Unit BOM survive your site survey with the NVLink and CDU numbers that match the datasheet you signed.
Create-only. Specs and dates from Supermicro’s Sep 23 Vera Rubin NVL72 shipping release, the same-day press page, and the Vera Rubin NVL72 datasheet. Rack, memory, NVLink, CDU, and Scalable Unit numbers are vendor claims until L11/L12 tickets and a named third-party pod publish. Update when the account team resolves the 216 vs 260 TB/s NVLink and 1.8 vs 2.2 MW CDU deltas in writing, or when a public BOM lists Scalable Unit storage and context-memory SKUs.
Sources: PR Newswire · Supermicro press · NVL72 datasheet.
Anpoo Sivanadi, Staff Software Engineer